1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with fault analysis function capable of testing a memory circuit such as a RAM incorporated therein and then performing fault analysis operation in detail.
2. Description of the Related Art
A conventional test circuit for testing a memory circuit portion incorporated in a semiconductor integrated circuit device is disclosed, for instance, in U.S. Pat. No. 5,815,512 (corresponding to a Japanese laid open publication No. JP-A-8/94718).
FIG. 1 is a circuit diagram showing a scan flip flop to be used in the test of a memory circuit such as a RAM (Random Access Memory). In FIG. 1, the reference numbers 2-5 and 291 each designates a scan flip flop (SFF), and 292 denotes a comparator incorporated in the scan flip flop (SFF) 291. This comparator 292 compares the output from a memory circuit D such as a RAM with an expected value EXP that has been prepared previously, and then outputs a comparison to the outside of the scan flip flop (SFF) 291. The reference number 293 indicates a flip flop (FF) for temporarily storing the comparison result transferred from the comparator 292.
FIG. 2 is a block diagram showing a RAM as a memory circuit and a conventional test circuit. In FIG. 2, the reference number 301 designates a RAM as a memory circuit, 291 denotes four scan flip flops connected in series that form a scan path to be used for a memory test operation of the RAM 301. The scan flip flop 291 is the same as the scan flip flop shown in FIG. 1 in configuration.
FIG. 3 is a diagram showing a configuration of the RAM 301 of 32 words and 4 bits as the object of test. In FIG. 3, the reference character WD designates a write-in driver circuit, SA denotes a sense amplifier, and 311 and 312 indicate a Y address decoder and a X address decoder, respectively. The reference number 313 designates each of column selectors, and 314 denotes each of memory cell groups G0 to G4. Each memory cell group 314 has thirty-two memory cells 0 to 31.
The reference character DI less than   greater than  (DI less than 0 greater than  to DI less than 3 greater than ) designates input data signals that are input through data input terminals to the RAM 301, and DO less than   greater than  (DO less than 0 greater than  to DO less than 3 greater than ) denotes output data signals that are output to outside of the RAM 301 through data output terminals.
The reference number A less than   greater than  (XA less than   greater than  and YA less than   greater than ) designates address signals that are input through address terminals to the RAM 301, and WE denotes a write enable signal that is input through the write enable terminal.
In general, as shown in FIG. 3, each memory cell group corresponding to one bit data input/output is arranged in a two dimension arrangement (for example, in a 4xc3x978 arrangement). Each of the memory cells in the memory cell group 314 in the RAM 301 shown in FIG. 3 is selected by using the X address (XA less than 2 greater than , XA less than 1 greater than  and XA less than 0 greater than ) and the Y address (YA less than 1 greater than  and YA less than 2 greater than ).
In each of the memory cell groups (G0 to G3) 314 in the RAM 301 shown in FIG. 3 comprises thirty-two memory cells (4xc3x978=32). Each of the memory cells is selected by one of addresses 0 to 31. For example, when the address signals are XA less than 2 greater than =1, XA less than 1 greater than =0, XA less than 0 greater than =1, and YA less than 1 greater than =1 and YA less than 0 greater than =0, the output X5 in the X decoder 312 is activated to select the output Y2 of each of the column selectors 313. As a result, the memory cell addressed by the address 32 in each of the memory cell group 314 is selected.
Next, a description will be given of the test operation for the conventional example.
In the RAM 301, the data output signals DO less than 0 greater than , DO less than 1 greater than , DO less than 2 greater than  and DO less than 3 greater than  of four bits that have been read from the memory cell groups (G0 to G3) 314 are output to corresponding flip flops 291 in the scan path shown in FIG. 2, respectively.
Because the four scan flip flips (SFF) 291 in the conventional example shown in FIG. 2 are connected in series, it takes four clocks to set the value 1 into all of the scan flip flops 291 in serial data transmission. As a result, the values of the output signals outputted from the scan flip flops 291 through the terminal SO becomes SO less than 0 greater than =1, SO less than 1 greater than =1, SO less than 2 greater than =1 and SO less than 3 greater than =1, respectively.
Next, both the control signals TM and SM are set to TM=1 and SM=1. In this situation, the test operation is executed by using all of the addresses of the RAM 301. That is to say, expected values EXP and a comparison control signal CMP are properly controlled while executing the write-in operation and read-out operation for all of the memory cells in the RAM 301 by using the all of the addresses. For example, the comparison instruction to initiate the comparison operation is given to the comparator 292 under CMP=1. As a result, because the value obtained through the data output terminal DO less than   greater than  from a defective memory cell in the RAM 301 is not equal to the expected value, the output of the comparator incorporated in the scan flip flop 291 (that corresponds to the comparator 292 shown in FIG. 1) becomes zero and the scan flip flop 291 corresponding to this comparator is reset to zero in synchronization with the clock signal T.
For example, when the scan flip flop (SFF less than 2 greater than ) 291 corresponding to the data output signal DO less than 2 greater than  from the memory cell in the RAM 301 detects a defective memory cell, the output signal from the scan flip flop (SFF less than 2 greater than ) 291 has the value of zero (SO less than 2 greater than =0). Other outputs from other scan flip flops (SFF less than 0 greater than , SFF less than 1 greater than , and SFF less than 3 greater than ) 291 maintain the value of one (SO less than 0 greater than =1, SO less than 1 greater than =1, and SO less than 3 greater than =1).
Next, both the control signals TM and SM are set to TM=0 and SM=1 and then test results SO less than 0 greater than  are shifted to the outside through the output terminal SO of the scan flip flop 291 in the final stage. When the test results are output serially, the output signal SO less than 0 greater than  becomes the serial output data SODO shown in FIG. 2.
Because the conventional semiconductor integrated circuit has the configuration described above, the test results from the memory cell group G3 are transferred to and then stored in the scan flip flop SFF less than 3 greater than , the test results from the memory cell group G2 are transferred to and then stored in the scan flip flop SFF less than 2 greater than , the test results from the memory cell group G1 are transferred to and then stored in the scan flip flop SFF less than 1 greater than , and the test results from the memory cell group G0 are transferred to and then stored in the scan flip flop SFF less than 0 greater than .
Accordingly, it is difficult to diagnose and distinguish a kind of defect in the conventional semiconductor integrated circuit device, for example, the defect is whether a fault of a single bit in a memory cell, of a bit line, or of a word line.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a semiconductor integrated circuit device with fault analysis function capable of efficiently performing the test operation for a memory section such as a RAM, and of easily performing a fault analysis in detail.
In accordance with one aspect of the present invention, a semiconductor integrated circuit device with fault analysis function has a memory circuit, a scan path and a comparison control circuit. The memory circuit has a plurality of memory cells that are divided into a plurality of memory cell groups in which data stored in the memory cells addressed by address signals are read and then output. The scan path has a plurality of scan flip flops placed corresponding to the plurality of memory cell groups. Each scan flip flop includes a comparator for comparing the data read from the memory cells with expected values that have been previously prepared and then outputting a comparison result. The comparison control circuit inputs control signals and the address signal. The comparison control circuit then generates a comparison control signal in order to initiate comparison operation between the data and the expected values by the comparators only when the memory cells addressed by the address signals are equal to memory cells of at least one or more in each memory cell group within a range specified by the control signals. Then, the comparison control circuit outputs the comparison control signal to each of the plurality of scan flip flops.
In this embodiment, the comparison control circuit outputs the comparison control signal to the plurality of scan flip flops in order to initiate comparison operation only for memory cells which are addressed by a specified single address.
In this embodiment, the comparison control circuit outputs the comparison control signal to the plurality of scan flip flops in order to initiate comparison operation for all of memory cells other than memory cells which are addressed by a specified single address.
In this embodiment, the comparison control circuit outputs the comparison control signal to the plurality of scan flip flops in order to initiate comparison operation for memory cells in the memory cell groups corresponding to a word line.
In this embodiment, the comparison control circuit outputs the comparison control signal to the plurality of scan flip flops in order to initiate comparison operation for memory cells in the memory cell groups addressed by a plurality of word lines the number of which is less than the number of all of word lines in each memory cell group.
In this embodiment, the memory cell groups having memory cells that are object memory cells for the comparison operation specified by the comparison control signal generated by and output from the comparison control circuit are addressed by a plurality of word lines that are adjacent to each other.
In this embodiment, the comparison control circuit outputs to the plurality of scan flip flops the comparison control signal in order to initiate comparison operation only for memory cells in the memory cell groups corresponding to word lines that are not adjacent to each other.
In this embodiment, the comparison control circuit outputs to the plurality of scan flip flops the comparison control signal in order to initiate comparison operation only for memory cells in each memory cell group corresponding to a bit line.
In this embodiment, the comparison control circuit outputs to the plurality of scan flip flops the comparison control signal in order to initiate comparison operation only for memory cells in each memory cell group corresponding to a plurality of bit lines.
In this embodiment, the memory cell groups having memory cells as object memory cells for comparison operation indicated by the comparison control signal generated by and output from the comparison control circuit are memory cell groups indicated by a plurality of bit lines that are adjacent to each other.
In this embodiment, the memory cell groups having memory cells as object memory cells for comparison operation indicated by the comparison control signal generated by and output from the comparison control circuit are memory cell groups indicated by bit lines other than a plurality of bit lines that are adjacent to each other.
In this embodiment, the comparison control circuit outputs to the plurality of scan flip flops the comparison control signal to initiate comparison operation only for alternate memory cells arranged in a lattice shape in each memory cell group.
In accordance with another aspect of the present invention, a semiconductor integrated circuit device with fault analysis function further has a repetitive control circuit for inputting the comparison result from the comparator incorporated in each of the plurality of scan flip flops. The repetitive control circuit generates a control signal to switch the memory cells specified by the comparison control signal output from the comparison control circuit according to the comparison result. Then, the repetitive control circuit outputs the control signal to the comparison control circuit in order to perform the comparison operation for the memory cells repeatedly.
A semiconductor integrated circuit device with fault analysis function in accordance with still another aspect of the present invention further has AND circuits arranged in first and second stages. The AND circuits in first stage perform AND operation between outputs from adjacent scan flip flops in the plurality of scan flip flops that form the scan path. The AND circuits in second stage perform AND operation between outputs from specified AND circuits in the AND circuits in first stage.
In accordance with another aspect of the present invention, a semiconductor integrated circuit device with fault analysis function further shift registers for providing the address signals serially and simultaneously to both the memory circuit and the comparison control circuit.
In this embodiment, the shift registers are placed corresponding to each of X address signals and Y address signals in the address signals.